Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for...

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• Resistive switching memory (RRAM) is crucial for energy-efficient pattern recognition using crossbar arrays.
• Achieving multilevel resistance states and a high on/off ratio in RRAM is essential for synaptic function.
• High negative voltages, while increasing the on/off ratio, can cause RRAM breakdown, leading to stuck-at-short faults.

Purpose of the Study:

• To address the challenge of RRAM breakdown and its impact on pattern recognition accuracy.
• To introduce a fault-tolerant scheme that mitigates the effects of RRAM failures without location identification.
• To verify the effectiveness of the proposed technique in non-ideal RRAM crossbar arrays.

Main Methods:

• Implementing a boost-factor adjustment technique for fault tolerance.
• Utilizing Spectre circuit simulation for verification.
• Testing the scheme on the Modified National Institute of Standards and Technology (NIST) dataset using convolutional neural networks.

Main Results:

• The boost-factor adjustment technique effectively suppresses RRAM failure interruptions.
• Spectre simulations demonstrated that the fault-tolerant scheme maintains recognition accuracy comparable to ideal RRAM arrays.
• The scheme operates without the need for identifying specific failed RRAM locations.

Conclusions:

• The proposed boost-factor adjustment technique offers a simple yet effective solution for fault tolerance in RRAM-based pattern recognition systems.
• This method significantly improves the robustness and reliability of neuromorphic computing architectures employing RRAM.
• The findings pave the way for more dependable and accurate AI hardware implementations.