EDSSA: An Encoder-Decoder Semantic Segmentation Networks Accelerator on OpenCL-Based FPGA Platform.

Area of Science:

• Computer Vision
• Hardware Acceleration
• Embedded Systems

Background:

• Visual semantic segmentation is crucial for applications like autonomous driving and robotics.
• Convolutional Neural Network (CNN)-based segmentation demands significant computing resources, unsuitable for power-constrained embedded devices.
• Graphics Processing Units (GPUs) often exceed the size and power budgets of terminal devices.

Purpose of the Study:

• To propose EDSSA, an Encoder-Decoder semantic segmentation network accelerator architecture for Field Programmable Gate Arrays (FPGAs).
• To demonstrate flexible parameter configuration and hardware resource utilization on Open Computing Language (OpenCL)-supported FPGA platforms.
• To evaluate the performance and energy efficiency of the proposed FPGA-based accelerator.

Main Methods:

• Developed EDSSA, an accelerator architecture for Encoder-Decoder semantic segmentation networks.
• Optimized the SegNet (an Encoder-Decoder network) algorithm for hardware implementation.
• Implemented and evaluated the architecture on an Intel Arria-10 GX1150 FPGA platform using OpenCL.

Main Results:

• Achieved a throughput exceeding 432.8 GOP/s on the Intel Arria-10 GX1150 platform.
• Demonstrated a power consumption of approximately 20 W.
• Reported a 1.2x improvement in energy-efficiency ratio compared to high-performance GPUs.

Conclusions:

• FPGA-based hardware systems provide a viable and power-efficient solution for semantic segmentation on embedded and terminal devices.
• EDSSA architecture enables flexible and resource-efficient implementation of semantic segmentation networks on FPGAs.
• The proposed solution significantly outperforms GPUs in terms of energy efficiency for this task.