An Improved VLSI Design of the ALU Based FIR Filter for Biomedical Image Filtering Application.

Area of Science:

• Digital Signal Processing (DSP)
• VLSI Design
• Image Processing

Background:

• Finite Impulse Response (FIR) filters are crucial in DSP and image processing, but traditional designs consume significant power.
• Area-efficient and low-power VLSI circuits are highly preferred for real-time applications.
• Existing FIR filter designs often involve complex adders and multipliers, increasing power consumption.

Purpose of the Study:

• To design an optimized Arithmetic Logic Unit (ALU)-based FIR filter structure.
• To reduce area, delay, and power consumption in FIR filter design.
• To enhance medical image processing, specifically retina image filtration, for improved visualization.

Main Methods:

• Implemented a latch-based clock-gating technique to reduce power consumption.
• Utilized XOR-based logic for reduced design complexity and area.
• Combined Carry Save Accumulator (CSA) and Ripple Carry Adder (RCA) for efficient addition, and employed a Booth multiplier algorithm with XOR logic for multiplication.

Main Results:

• The proposed ALU-based FIR filter with clock-gating achieved significant reductions in static and dynamic power consumption.
• Modified adders (CSA+RCA) and an enhanced Booth multiplier reduced delay and area utilization.
• The design demonstrated improved Mean Squared Error (MSE) and Peak Signal-to-Noise Ratio (PSNR) for retina image processing compared to existing methods.

Conclusions:

• The developed ALU-based FIR filter with latch-based clock gating offers an efficient solution for medical image processing.
• The optimized design successfully balances power, delay, and area, leading to enhanced image visualization.
• The methodology provides a robust VLSI model for high-performance digital filtering in medical applications.