Noise Optimization Techniques for Switched-Capacitor Based Neural Interfaces.

Area of Science:

• Biomedical Engineering
• Electrical Engineering
• Neuroscience

Background:

• Neural interfaces are crucial for brain-computer interfaces and neurological research.
• Conventional switched-capacitor (SC) architectures face challenges with noise, limiting their application range.
• Minimizing noise is essential for accurate recording of neural signals like local field potentials (LFPs) and extracellular spikes.

Purpose of the Study:

• To present noise optimization techniques for a novel SC-based neural interface architecture.
• To demonstrate the circuit implementation and performance of the optimized neural interface.
• To validate the effectiveness of the noise reduction strategies through experimental testing.

Main Methods:

• Development of a parasitic capacitance suppression scheme to minimize noise charge transfer.
• Implementation of a recording path-splitting scheme for selective signal recording (LFPs, spikes, or both) and reduced noise floor.
• Integration of an auto-zero noise cancellation scheme to suppress kT/C noise in the neural amplifier.
• Fabrication and testing of a prototype neural interface chip using a 0.13 μm CMOS process.

Main Results:

• The designed chip exhibits an input-referred noise of 4.8 μV from 1 Hz to 300 Hz and 2.3 μV from 300 Hz to 8 kHz.
• In-vivo experiments show a total noise floor (including neural activity and electrode noise) of approximately 20 μV peak-to-peak.
• The proposed noise optimization techniques effectively reduce the circuit noise floor compared to conventional architectures.

Conclusions:

• The developed noise optimization techniques significantly improve the performance of SC-based neural interfaces.
• The optimized architecture enables a wider application range for SC circuits in neural recording.
• Experimental validation confirms the efficacy of the proposed methods in reducing noise for both bench-top and in-vivo scenarios.