Random-telegraph-noise-enabled true random number generator for hardware security.

Area of Science:

• Cyber-security
• Integrated Circuit Design
• Random Number Generation

Background:

• Internet of Things (IoT) security relies on robust random number generation.
• Existing True Random Number Generators (TRNGs) face limitations in output bit rate, power consumption, and design complexity.
• Conventional CMOS technology is crucial for power- and area-constrained security applications.

Purpose of the Study:

• To present a novel, experimentally verified TRNG utilizing conventional CMOS technology.
• To address limitations in existing TRNG designs regarding complexity, output bit rate, and power consumption.
• To enhance the security of Internet of Things devices through efficient random number generation.

Main Methods:

• Utilizing the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source.
• Implementing multi-level and abnormal telegraph noise for improved device selectivity and higher bitrates.
• Verifying the design using a breadboard and a Field-Programmable Gate Array (FPGA) proof-of-concept circuit.

Main Results:

• The novel TRNG design demonstrates key improvements in complexity, output bit rate, and power consumption compared to previous designs.
• The design successfully passes all 15 NIST randomness tests without requiring post-processing.
• The generated bitstream shows resilience against sophisticated machine learning attacks, specifically using LSTM neural networks.

Conclusions:

• The presented CMOS-based TRNG offers a significant advancement for secure and efficient random number generation in constrained environments.
• The utilization of telegraph noise, including multi-level and abnormal types, provides a highly effective entropy source.
• The design's robustness and performance make it a promising solution for enhancing the future security of Internet of Things devices.