Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

Area of Science:

• Electrical Engineering
• Signal Processing
• Image Sensor Technology

Background:

• Time-mode analog-to-digital converters (ADCs) are crucial for imagers with parallel acquisition.
• Compensation of dark signal non-uniformity (DSNU) and photo-response non-uniformity (PRNU) is critical for image quality.
• Fixed pattern noise (FPN) degrades image fidelity in such systems.

Purpose of the Study:

• To propose a digital clock stopping technique for gain and offset correction in time-mode ADCs.
• To address the critical need for DSNU and PRNU compensation in massively parallel imagers.
• To enhance the linearity and reduce fixed pattern noise in CMOS imagers.

Main Methods:

• Implementation of a digital clock stopping technique for precise gain and offset correction.
• Application of the technique to time-mode ADCs in imagers requiring parallel data acquisition.
• Experimental validation using a 128-pixel CMOS imager.

Main Results:

• Achieved significant reduction in photo-response non-uniformity (PRNU) to approximately 0.5 least significant bit (LSB).
• Demonstrated substantial fixed pattern noise (FPN) reduction.
• Implemented a linearity improvement technique, reducing integral nonlinearity (INL) to about 0.5 LSB.

Conclusions:

• The proposed digital clock stopping technique effectively corrects gain and offset errors in time-mode ADCs.
• The method significantly reduces image sensor noise (DSNU, PRNU, FPN) and improves linearity (INL).
• Experimental results confirm the effectiveness and applicability of the proposed approach for advanced imaging systems.