In-Built N⁺ Pocket Electrically Doped Tunnel FET With Improved DC and Analog/RF Performance

In this paper, we present an in-built N⁺ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate (CG) and a polarity gate (PG). The PG is biased at -0.7 V to induce a P⁺ region at the source side, leaving an N⁺ pocket between the source and the channel. This technique yields an N⁺ pocket that is realized in the in-built architecture and removes the need for additional chemical doping. Calibrated 2-D simulations have demonstrated that the introduction of the N⁺ pocket yields a higher I_ON and a steeper average subthreshold swing when compared to conventional ED-TFET. Further, a local minimum on the conduction band edge (E_C) curve at the tunneling junction is observed, leading to a dramatic reduction in the tunneling width. As a result, the in-built N⁺ pocket ED-TFET significantly improves the DC and analog/RF figure-of-merits and, hence, can serve as a better candidate for low-power applications.