High-Performance Top-Gate Thin-Film Transistor with an Ultra-Thin Channel Layer

Area of Science:

• Materials Science
• Semiconductor Physics
• Device Engineering

Background:

• Metal-oxide thin-film transistors (TFTs) are vital for display panels but require enhanced electron mobility.
• Existing TFTs face limitations in achieving the high performance needed for next-generation electronic applications.

Purpose of the Study:

• To develop high-performance top-gate coplanar binary tin oxide (SnO2) thin-film transistors (TFTs).
• To investigate the impact of device architecture and interface engineering on TFT performance.

Main Methods:

• Fabrication of top-gate coplanar SnO2 TFTs using an ultra-thin SnO2 channel (4.5 nm).
• Incorporation of a HfO2 gate dielectric with a 3 nm SiO2 interfacial layer.
• Characterization of device performance, including field-effect mobility (μ), on/off current ratio (ION/IOFF), and subthreshold slope.

Main Results:

• Achieved a high field-effect mobility (μ) of 136 cm²/Vs, a record for top-gate TFTs on amorphous SiO2 substrates processed at ≤ 400 °C.
• Obtained a large on-current/off-current (ION/IOFF) ratio of 1.5 × 10⁸ and a steep subthreshold slope of 108 mV/dec.
• Demonstrated that the SiO2 interfacial layer is critical for reducing defect scattering and enhancing mobility.

Conclusions:

• The optimized top-gate coplanar SnO2 TFTs exhibit excellent performance metrics.
• The findings are significant for advancing applications in displays, dynamic random-access memory (DRAM), and monolithic 3D integrated circuits (ICs).
• Interface engineering with a SiO2 layer is key to unlocking the potential of SnO2-based electronics.