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Efficient implementation of LMS adaptive filter-based FECG extraction on an FPGA
Bhavya Vasudeva1, Puneesh Deora1, Pradhan Mohan Pradhan1
1Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Uttarakhand, India.
This study presents a Field Programmable Gate Array (FPGA) implementation for fetal heart rate (FHR) monitoring. The system accurately extracts fetal electrocardiograms (FECG) using an adaptive filter, improving precision and reducing hardware resource utilization.
Area of Science:
- Biomedical Engineering
- Digital Signal Processing
- Hardware Implementation
Background:
- Accurate fetal heart rate (FHR) monitoring is crucial for prenatal care.
- Existing methods for fetal electrocardiogram (FECG) extraction face challenges in noise reduction and computational efficiency.
- Field Programmable Gate Arrays (FPGAs) offer a flexible platform for developing real-time biomedical signal processing systems.
Purpose of the Study:
- To develop and implement an FPGA-based system for fetal heart rate (FHR) monitoring.
- To enhance the accuracy and precision of FECG extraction and FHR detection.
- To propose and evaluate two distinct architectures for the Least Mean Squares Adaptive Filter (LMS-AF) for FECG extraction.
Main Methods:
- Implementation of a preprocessing unit for noise removal.
- Development of a foetal electrocardiogram (FECG) extraction unit utilizing a Least Mean Squares Adaptive Filter (LMS-AF).
- Design of two LMS-AF architectures (series and parallel) on FPGA, including a floating-point unit for improved arithmetic operations.
Main Results:
- The system achieved high sensitivity (95.74-100%) and specificity (100%) in detecting R peaks from extracted FECG.
- The parallel LMS-AF architecture demonstrated up to an 85.88% reduction in convergence time.
- The series LMS-AF architecture showed a 27.41% reduction in hardware resource utilization (flip-flops).
- An overall accuracy increase of 2-7.51% was observed compared to previous works.
Conclusions:
- The proposed FPGA-based system provides an effective and efficient solution for fetal heart rate monitoring.
- The parallel architecture optimizes convergence time and power consumption, while the series architecture minimizes hardware resource usage.
- This work contributes to advancing non-invasive FECG extraction techniques with improved performance metrics.
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