Mapping of integrated PIN diodes with a 3D architecture by scanning microwave impedance microscopy and dynamic...

This work addresses the need for a comprehensive methodology for nanoscale electrical testing dedicated to the analysis of both "front end of line" (FEOL) (doped semiconducting layers) and "back end of line" (BEOL) layers (metallization, trench dielectric, and isolation) of highly integrated microelectronic devices. Based on atomic force microscopy, an electromagnetically shielded and electrically conductive tip is used in scanning microwave impedance microscopy (sMIM). sMIM allows for the characterization of the local electrical properties through the analysis of the microwave impedance of the metal-insulator-semiconductor nanocapacitor (nano-MIS capacitor) that is formed by tip and sample. A highly integrated monolithic silicon PIN diode with a 3D architecture is analysed. sMIM measurements of the different layers of the PIN diode are presented and discussed in terms of detection mechanism, sensitivity, and precision. In the second part, supported by analytic calculations of the equivalent nano-MIS capacitor, a new multidimensional approach, including a complete parametric investigation, is performed with a dynamic spectroscopy method. The results emphasize the strong impact, in terms of distinction and location, of the applied bias on the local sMIM measurements for both FEOL and BEOL layers.