Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction.

Area of Science:

• Neuroscience
• Computer Engineering
• Biomedical Engineering

Background:

• Wearable electroencephalogram (EEG) systems offer potential for continuous brain monitoring.
• Real-time analysis of functional connectivity (FC) is crucial for advanced neurofeedback.
• Existing methods often face computational limitations for real-time processing.

Purpose of the Study:

• To design a novel hardware architecture for real-time quantitative characterization of FC networks.
• To optimize algorithms for calculating FC and graph-theoretic parameters for hardware implementation.
• To enable efficient processing of EEG data for wearable applications.

Main Methods:

• Algorithm-to-architecture mapping for phase lag index calculation to form FC networks.
• Extraction of graph-theoretic parameters for quantitative network characterization.
• Optimization of mathematical definitions to reduce computational complexity and enhance hardware compatibility.

Main Results:

• Developed a 19-channel EEG system architecture.
• Achieved real-time calculation of FC parameters in 131 µs.
• FPGA implementation (Stratix IV) utilized 71% logic resources with 51.84 mW dynamic power at 22.16 MHz.
• Estimated ASIC implementation (90 nm CMOS) power consumption of 39.3 mW at 0.9 V.

Conclusions:

• The proposed architecture enables real-time FC calculation and parameter extraction with low power consumption.
• Ideal for wearable closed-loop neurofeedback systems requiring continuous EEG monitoring and fast processing.
• Facilitates immediate feedback control based on brain activity analysis.