Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Concept Videos

MOS Capacitor01:25

MOS Capacitor

1.2K
A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
1.2K
Semiconductors01:22

Semiconductors

1.1K
There is variation in the electrical conductivity of materials - metals, semiconductors, and insulators that are showcased with the help of the energy band diagrams.
Metals such as copper (Cu), zinc (Zn), or lead (Pb) have low resistivity and feature conduction bands that are either not fully occupied or overlap with the valence band, making a bandgap non-existent. This allows electrons in the highest energy levels of the valence band to easily transition to the conduction band upon gaining...
1.1K
Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

430
Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
430
Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

1.2K
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
1.2K
System of Memory01:23

System of Memory

6.9K
Memory is categorized into three major systems: sensory memory, short-term memory (STM), and long-term memory (LTM). These systems differ in their capacity and the duration for which they can hold information. Sensory memory captures raw sensory input from the environment, holding it for just a few seconds or less. For example, on hearing a brief, loud sound, like a car horn honking, the sound seems to linger in the mind for a moment even after it stops. This is an instance of sensory memory...
6.9K
Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

671
The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The...
671

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

Low breakdown field and high ionization index in ReSe<sub>2</sub> avalanche field-effect transistors.

Nature communications·2026
Same author

Coupled ferroelectric-anisotropic optoelectronic synapse for polarization-sensitive neuromorphic vision.

Nature communications·2026
Same author

High-density conductance states and synaptic plasticity in SnP<sub>2</sub>S<sub>6</sub> memristors for neuromorphic computing.

Nanoscale horizons·2025
Same author

Wafer-Scale Monolayer MoS<sub>2</sub> with Tunable Grain Size via Grain Boundary Engineering for Neuromorphic Computing.

ACS nano·2025
Same author

AI-driven advances in metal-organic frameworks: from data to design and applications.

Chemical communications (Cambridge, England)·2025
Same author

Wafer-scale integration of monolayer MoS<sub>2</sub><i>via</i> residue-free support layer etching and angular strain suppression.

Nanoscale·2025
Same journal

Engineered Young Brown Adipose Tissue-Derived Exosomes Alleviate Radiation-Induced Lung Injury by Promoting G Protein-Coupled Receptor 183 Ubiquitination.

ACS nano·2026
Same journal

Pore Geometry-Driven Capture of Trace Aromatic Volatile Organic Compounds in Al-Based MOFs.

ACS nano·2026
Same journal

Dual-Bridged Porphyrin-Based Covalent Organic Framework with Integrated Specific Fluorescent Recognition and Cooperative Adsorption Capabilities.

ACS nano·2026
Same journal

Split-Gate Memtransistors for Energy-Efficient Adaptive Reinforcement Learning.

ACS nano·2026
Same journal

Interface Coordination Nucleation of Copper Nanoclusters on Covalent Organic Frameworks for Electrocatalytic Ammonia Synthesis.

ACS nano·2026
Same journal

High-Performance Near-Infrared Quantum Emission from Color Centers in hBN.

ACS nano·2026
See all related articles

Related Experiment Video

Updated: Nov 21, 2025

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

8.2K

Self-Selective Multi-Terminal Memtransistor Crossbar Array for In-Memory Computing.

Xuewei Feng1, Sifan Li1, Swee Liang Wong2

  • 1Department of Electrical and Computer Engineering, National University of Singapore, 117583, Singapore.

ACS Nano
|January 14, 2021
PubMed
Summary
This summary is machine-generated.

This study introduces a novel memtransistor crossbar array that overcomes issues in resistive switching devices. The new design enables efficient in-situ computation for AI and IoT applications with high accuracy.

Keywords:
MoS2in-memory computingmemtransistormulti-terminalself-selective

More Related Videos

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
09:49

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

4.2K
Micro-drive Array for Chronic in vivo Recording: Tetrode Assembly
14:19

Micro-drive Array for Chronic in vivo Recording: Tetrode Assembly

Published on: April 22, 2009

33.8K

Related Experiment Videos

Last Updated: Nov 21, 2025

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
08:07

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes

Published on: March 9, 2019

8.2K
In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
09:49

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

4.2K
Micro-drive Array for Chronic in vivo Recording: Tetrode Assembly
14:19

Micro-drive Array for Chronic in vivo Recording: Tetrode Assembly

Published on: April 22, 2009

33.8K

Area of Science:

  • Materials Science
  • Electrical Engineering
  • Computer Science

Background:

  • Two-terminal resistive switching devices suffer from interdevice variability and sneak currents, causing errors and high power consumption.
  • Existing solutions like the one-transistor-one-RRAM (1T-1R) configuration mitigate crosstalk but increase circuit footprint.

Purpose of the Study:

  • To develop a multi-terminal memtransistor crossbar array that enhances parallelism and enables in-situ computation.
  • To address the limitations of traditional resistive switching devices for AI and IoT applications.

Main Methods:

  • Demonstration of a multi-terminal memtransistor crossbar array with independent gate control for programming parallelism.
  • Utilizing a dense cell size (3-4.5 F²) and achieving minimal sneak current (0.1 nA).

Main Results:

  • Achieved a low switching energy of 20 fJ/bit at 0.42 V.
  • Demonstrated capability for multiply-and-accumulate operations, crucial for pattern classification.
  • Simulated high MNIST recognition accuracy of 96.87% due to linear synaptic plasticity.

Conclusions:

  • The proposed memtransistor crossbar array offers a revolutionary computing paradigm for data-centric AI and IoT.
  • This architecture overcomes key challenges in resistive switching, paving the way for denser and more efficient computing systems.