Engineering an Indium Selenide van der Waals Interface for Multilevel Charge Storage.

Area of Science:

• Materials Science
• Solid-State Physics
• Nanotechnology

Background:

• Floating-gate transistors face physical limitations due to continuous miniaturization.
• Novel device architectures and materials are crucial for next-generation nonvolatile memory.

Purpose of the Study:

• To demonstrate a new nonvolatile memory structure utilizing a van der Waals gate architecture.
• To explore the potential of indium selenide (InSe) for multilevel data storage.

Main Methods:

• Fabrication of a van der Waals gate architecture with a partially oxidized surface layer/InSe interface.
• Indirect oxygen plasma treatment to create charge-trapping sites on the InSe surface.
• Operando scanning X-ray photoelectron spectroscopy and Kelvin probe microscopy to analyze device characteristics.

Main Results:

• The device achieved multilevel data storage with eight distinct states retained over 3000 seconds.
• A high current switching ratio of 10^6 was observed within 11 cycles.
• Charge retention without a gate dielectric was demonstrated, attributed to engineered InSe interface properties.

Conclusions:

• The engineered InSe interface enables nonvolatile memory functionality through charge-trapping sites and van der Waals gating.
• This approach offers a promising alternative to conventional floating-gate memory technologies.
• The device's characteristics suggest significant potential for advanced nonvolatile memory applications.