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Related Concept Videos

Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

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The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
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Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
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In most substances, the current flow is proportional to the voltage applied to it. A simple relationship between the values of current, voltage, and resistance is known as Ohm's law. Nonohmic devices do not exhibit a linear relationship between voltage and current. One such device is the semiconducting circuit element known as a diode. A diode is a circuit device that allows current flow in only one direction.
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Residue-Free Fabrication of van der Waals Heterostructures of Two-Dimensional Materials
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Satisfiability Attack-Resistant Camouflaged Two-Dimensional Heterostructure Devices.

Akshay Wali1, Shamik Kundu2, Andrew J Arnold1

  • 1Department of Electrical Engineering, Pennsylvania State University, University Park, Pennsylvania 16802, United States.

ACS Nano
|January 28, 2021
PubMed
Summary
This summary is machine-generated.

This study introduces novel 2D heterostructure devices for area-efficient integrated circuit camouflaging, offering superior resilience against reverse engineering attacks compared to traditional methods.

Keywords:
camouflagingintegrated circuitreverse engineeringsecuritytwo-dimensional materials

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Area of Science:

  • Materials Science and Engineering
  • Electrical Engineering
  • Computer Security

Background:

  • Globalized semiconductor supply chains introduce security risks like reverse engineering (RE).
  • Existing integrated circuit (IC) camouflaging techniques, such as transformable interconnects and covert gates, have limitations.
  • Current solutions face challenges with area overhead and vulnerability to satisfiability solver (SAT)-based RE attacks.

Purpose of the Study:

  • To develop area-efficient and SAT-resilient IC camouflaging solutions.
  • To leverage the unique properties of two-dimensional (2D) transition-metal dichalcogenides (TMDs) and transition-metal oxides (TMOs).
  • To demonstrate enhanced hardware security against reverse engineering.

Main Methods:

  • Utilized 2D TMDs (MoS2, MoSe2, MoTe2, WS2, WSe2) and optically transparent TMOs to engineer heterostructures.
  • Demonstrated the creation of camouflaged resistors, diodes, and field-effect transistors (FETs) with tunable electrical properties.
  • Applied these 2D heterostructure devices for camouflaging both digital and analog circuits, including NAND, NOR, AND, and OR gates.

Main Results:

  • Achieved area-efficient camouflaging with significantly less overhead compared to complementary metal oxide semiconductor (CMOS)-based methods (100% logic obfuscation vs. 5%).
  • Engineered devices exhibit properties like resistors with 5 orders of magnitude resistance difference and FETs with adjustable characteristics.
  • Camouflaged circuits using 2D heterostructures demonstrated invulnerability to SAT attacks for over 10 hours, unlike CMOS-based circuits decamouflaged in <40 minutes.

Conclusions:

  • 2D heterostructure devices offer a highly resilient and area-efficient solution for integrated circuit camouflaging.
  • This approach provides robust protection against advanced reverse engineering techniques, including SAT and automatic test pattern generation attacks.
  • The cross-layer optimization connecting material properties to device design highlights a novel strategy for securing hardware.