FPGA-Based High-Throughput CNN Hardware Accelerator With High Computing Resource Utilization Ratio.

Area of Science:

• Computer Engineering
• Hardware Acceleration
• Artificial Intelligence

Background:

• Field-Programmable Gate Array (FPGA)-based Convolutional Neural Network (CNN) hardware accelerators are gaining attention.
• Existing single- and multi-computing engine (CE) architectures suffer from throughput limitations due to inefficient resource mapping and data supply.

Purpose of the Study:

• To propose a novel composite hardware CNN accelerator architecture to overcome existing throughput limitations.
• To enhance the efficiency of both convolution layers (CL) and fully connected layers (FCL) in CNN hardware acceleration.

Main Methods:

• A novel multi-CE architecture with a row-level pipelined streaming strategy for efficient CL processing.
• Optimized mapping mechanisms and continuous data supply systems for each CE to maximize resource utilization.
• A weight data allocation strategy to reduce off-chip bandwidth stress and a single-CE architecture with batch-based computing for FCL.

Main Results:

• Implementation of Visual Geometry Group network-16 (VGG-16) achieved 1 TOPS throughput at 150 MHz, reaching 98.15% of theoretical throughput.
• ResNet-101 accelerator attained 600 GOPS at 100 MHz, achieving 96.12% of theoretical throughput.
• Both accelerators were implemented on the XC7VX980T FPGA platform.

Conclusions:

• The proposed composite hardware CNN accelerator architecture effectively addresses resource mapping and data supply issues.
• The design achieves high throughput and near-theoretical performance for complex CNN models like VGG-16 and ResNet-101 on FPGAs.