Efficient FPGA implementation of high-speed true random number generator.

Area of Science:

• Information Security
• Hardware Security
• Cryptography

Background:

• High-speed true random number generators (TRNGs) are critical for modern information security.
• Existing TRNGs face challenges in balancing speed, resource consumption, and security.
• Self-timed rings (STRs) are a common entropy source for TRNGs.

Purpose of the Study:

• To propose and demonstrate an efficient high-speed TRNG.
• To enhance security by evaluating randomness using min-entropy and employing a Toeplitz-hashing extractor.
• To optimize hardware resource usage and data throughput on field-programmable gate arrays (FPGAs).

Main Methods:

• Utilizing multiple parallel self-timed rings (STRs) as the entropy source.
• Implementing an information-theoretically secure Toeplitz-hashing extractor.
• Systematically analyzing the trade-offs between throughput and resource consumption based on system parameters.
• Jointly optimizing the degree of parallelism of STRs and extractor efficiency.

Main Results:

• A 10-Gbps TRNG was efficiently implemented.
• The generator's output successfully passed all National Institute of Standards and Technology (NIST) and Dieharder test suites.
• The proposed design demonstrates a favorable balance between high throughput and efficient resource utilization.

Conclusions:

• The developed parallel STR-based TRNG offers a practical solution for high-speed, secure random number generation.
• The optimization strategy effectively addresses the constraints of FPGA implementation.
• The TRNG meets stringent randomness requirements for demanding information security applications.