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Summary

This summary is machine-generated.

This study introduces defect-driven gradient-based optimization for computational lithography. The method ensures defect-free chip printing within practical runtime, overcoming challenges with large data sizes.

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Area of Science:

Computational lithography
Semiconductor manufacturing
Image processing

Background:

Optimized imaging solutions in computational lithography require defect-free printing checks.
Current methods face challenges with large chip layout data, impacting runtime and storage.
Integrating defect detection into the optimization process is highly desirable.

Purpose of the Study:

To develop a gradient-based optimization scheme driven by defect detection.
To address the challenges of large data sizes in computational lithography optimization.
To achieve defect-free lithography printing within practical runtime specifications.

Main Methods:

Demonstration of defect-driven gradient-based optimization.
Utilizing ASML's Tachyon SMO computational lithography product.
Implementing a mechanism for defect detection within the optimization loop.

Main Results:

Achieved a defect-free lithography printing solution.
Optimization process completed within practical runtime specifications.
Successfully addressed challenges related to large chip layout data.

Conclusions:

Defect-driven gradient-based optimization is a viable approach for computational lithography.
The demonstrated technology enables efficient and defect-free chip manufacturing.
ASML's Tachyon SMO facilitates practical implementation of this advanced optimization technique.