Hardware Design for Autonomous Bayesian Networks

Area of Science:

• Artificial Intelligence
• Computer Engineering
• Computational Neuroscience

Background:

• Bayesian networks are crucial for probabilistic inference and causal reasoning in AI.
• Current implementations often require sequencers for sequential p-bit updates, increasing complexity.
• Stochastic artificial neural networks utilize probabilistic bits (p-bits) analogous to biological neurons.

Purpose of the Study:

• To investigate the feasibility of autonomous hardware Bayesian networks operating without clocks or sequencers.
• To present a behavioral model for simulating large-scale sequencer-free networks.
• To explore the potential of energy-efficient hardware accelerators for Bayesian networks.

Main Methods:

• SPICE simulations were used to validate the operation of autonomous hardware Bayesian networks.
• A behavioral model was developed and benchmarked against SPICE simulations.
• The design of individual p-bits was optimized for autonomous, sequencer-free functionality.

Main Results:

• SPICE simulations confirmed that appropriately designed p-bits enable autonomous hardware Bayesian networks to function correctly without clocks or sequencers.
• A behavioral model accurately represents the essential characteristics for sequencer-free operation.
• The proposed hardware architecture supports massively parallel, autonomous operation.

Conclusions:

• Autonomous hardware Bayesian networks can be realized without clocks or sequencers through optimized p-bit design.
• The developed behavioral model facilitates the simulation of large-scale networks.
• This research offers a pathway towards energy-efficient hardware accelerators with relevance to biological neural dynamics.