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An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori
Hasnain Raza1, Syed Azhar Ali Zaidi1, Aamir Rashid1
1Electronics Engineering Department, Faculty of Electronics and Electrical Engineering, University of Engineering and Technology, Taxila, Pakistan.
Plos One
|March 29, 2021
Summary
This study introduces a low-complexity algorithm for decoding Low-Density Parity-Check (LDPC) codes, achieving significant improvements in area efficiency and speed for next-generation communication systems.
Area of Science:
- Electrical Engineering
- Computer Science
- Information Theory
Background:
- High-speed communication standards require efficient forward error correction decoders.
- Low-Density Parity-Check (LDPC) codes are crucial for reliable data transmission.
Purpose of the Study:
- To develop a low-complexity decoding algorithm for LDPC codes.
- To optimize the hardware implementation for area efficiency and high throughput.
Main Methods:
- Explored the min-sum iterative construction a posteriori probability (MS-IC-APP) algorithm.
- Performed error performance analysis for a (648,1296) regular QC-LDPC code.
- Proposed a layered scheduling and architecture-level optimizations for hardware implementation.
Main Results:
- The MS-IC-APP decoder achieved 6.95 times less area and 4 times higher throughput than the standard min-sum decoder.
- Area and throughput are comparable to improved hard-decision bit-flipping (BF) decoders.
- A coding gain of 2.5 was observed over the best BF decoder implementation.
Conclusions:
- The MS-IC-APP algorithm offers a promising solution for area-efficient and high-speed LDPC decoding.
- Optimized hardware implementation significantly enhances decoder performance.
- The proposed method provides superior error performance compared to existing bit-flipping decoders.
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