Exploiting Computation Reuse for Stencil Accelerators.

Area of Science:

• Computer Science
• Hardware Acceleration
• Algorithm Optimization

Background:

• Stencil kernels are crucial in many applications, with ongoing research in parallelization and reuse optimizations.
• Existing methods face challenges in computation reuse for accelerators due to incomplete design-space exploration.

Purpose of the Study:

• To address computation reuse challenges for stencil kernels with reduction operations on accelerators.
• To develop efficient algorithms for design-space exploration and pruning in stencil kernel synthesis.

Main Methods:

• Formal definition of the complete design space for stencil kernels with flexible computation reuse.
• Development of a provably optimal dynamic programming algorithm.
• Implementation of a heuristic beam search algorithm using an architecture-aware model.

Main Results:

• Significant reduction in hardware resource usage: 58.1% LUT and 54.6% DSP reduction on FPGAs compared to state-of-the-art compilers.
• Achieved an average speedup of 2.3× for compute-intensive kernels.
• Outperformed latest CPU/GPU results in performance.

Conclusions:

• The proposed algorithms effectively optimize stencil kernels with reduction operations for accelerators.
• The methods provide significant improvements in hardware efficiency and computational speed.
• This work advances the state-of-the-art in stencil kernel synthesis for FPGAs.