Addressing multiple bit/symbol errors in DRAM subsystem

Area of Science:

• Computer Engineering
• Data Storage Technologies
• Fault-Tolerant Systems

Background:

• DRAM technology scaling increases fault severity.
• Existing CHIPKILL schemes have limitations in detecting multiple symbol errors from various faults.
• Silent Data Corruptions (SDCs) pose a significant risk in modern servers.

Purpose of the Study:

• Introduce a novel error handling scheme, Single Symbol Correction Multiple Symbol Detection (SSCMSD).
• Address the limitations of current error correction methods in DRAM subsystems.
• Enhance data integrity and system reliability against complex fault scenarios.

Main Methods:

• Developed SSCMSD scheme combining hashing with Error Correcting Code (ECC).
• Implemented SSCMSD using a 32-bit Cyclic Redundancy Check (CRC) and Reed-Solomon code for DDR4 systems.
• Utilized simulation-based experiments to validate the scheme's effectiveness.

Main Results:

• The SSCMSD scheme effectively corrects single-symbol errors and detects multi-symbol errors.
• Successfully guarded against device, data-bus, and address-bus errors.
• Achieved robust error detection without introducing additional READ latency.

Conclusions:

• SSCMSD provides a robust solution against diverse DRAM subsystem faults, mitigating SDCs.
• The scheme's effectiveness is primarily limited by hash aliasing probability.
• This approach offers enhanced data protection for high-density DRAM systems without performance degradation.