AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs.

Area of Science:

• Computer Engineering
• Hardware Design
• VLSI

Background:

• High-Level Synthesis (HLS) offers design productivity but lags in achievable frequency compared to handcrafted Register-Transfer Level (RTL) designs.
• Accurate interconnect delay estimation in HLS is challenging, particularly for large designs on multi-die FPGAs, limiting timing performance.

Purpose of the Study:

• To address the timing gap in HLS designs by improving frequency and routability on multi-die FPGAs.
• To introduce an automated framework, AutoBridge, that integrates floorplanning and pipelining into the HLS compilation flow.

Main Methods:

• AutoBridge couples coarse-grained floorplanning with pipelining during HLS compilation.
• It provides HLS with global physical layout information to identify and pipeline long wires, especially across die boundaries.
• Exploits HLS pipelining flexibility for logic distribution across multiple dies, preventing single-die congestion and timing degradation.

Main Results:

• Achieved a 102% average frequency improvement, from 147 MHz to 297 MHz, across 43 design configurations.
• Enabled 16 previously unroutable designs to achieve an average frequency of 274 MHz.
• Maintained throughput and showed negligible changes in resource utilization.

Conclusions:

• AutoBridge effectively bridges the frequency gap between HLS and RTL designs on multi-die FPGAs.
• The framework enhances timing quality by intelligently managing interconnect delays and logic placement.
• AutoBridge is a valuable addition to existing CAD toolflows for Xilinx FPGAs.