A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Convolutional Neural Networks (CNNs) excel at image classification but require significant computational power for real-time inference.
• Graphics Processing Units (GPUs) are often power-prohibitive for mobile devices, making Field-Programmable Gate Arrays (FPGAs) a viable alternative for high-speed inference.
• Existing FPGA CNN implementations face challenges with high on-chip memory and arithmetic resource demands, limiting their use on resource-constrained edge devices.

Purpose of the Study:

• To develop a scalable, low-power, and resource-efficient accelerator architecture for MobileNet V2 CNN inference.
• To address the limitations of current FPGA-based CNN accelerators for edge computing applications.

Main Methods:

• Designed a heterogeneous system integrating an embedded processor, external memory, and reconfigurable logic with scalable Processing Elements (PEs).
• Implemented the accelerator architecture on a XCZU7EV FPGA operating at 200 MHz.
• Utilized a scalable number of PEs for adaptable performance.

Main Results:

• Achieved 87% top-5 accuracy for MobileNet V2 inference.
• Processed a 224x224 pixel image in 220 ms.
• Consumed only 7.35 W of power.
• Required less than 30% of the logic and arithmetic resources compared to other MobileNet FPGA accelerators.

Conclusions:

• The proposed FPGA accelerator architecture offers a significant improvement in power and resource efficiency for MobileNet V2 inference.
• This design is well-suited for real-time image classification tasks on resource-constrained edge devices.
• The scalability of the Processing Elements allows for flexible deployment across various edge computing scenarios.