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This study introduces a mixed-precision weights network (MPWN), a novel quantization neural network. MPWN significantly reduces hardware resource usage and latency compared to traditional models.

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Area of Science:

  • Computer Science
  • Artificial Intelligence
  • Machine Learning

Background:

  • Deep learning models often require substantial computational resources.
  • Quantization techniques aim to reduce model size and improve efficiency.
  • Existing methods may not fully exploit diverse weight precision levels.

Purpose of the Study:

  • To introduce a mixed-precision weights network (MPWN) that integrates binary, ternary, and 32-bit floating-point weight spaces.
  • To develop software and hardware optimizations for the MPWN.
  • To evaluate the efficiency and performance of the MPWN.

Main Methods:

  • Developed a mixed-precision weights network (MPWN) combining binary, ternary, and 32-bit floating-point weights.
  • Introduced an accuracy sparsity bit score for efficient Bayesian optimization of weight space combinations.
  • Proposed XOR signed-bits for efficient hardware implementation of mixed-precision multiplications.
  • Implemented the MPWN on a field-programmable gate array (FPGA) using high-level synthesis.

Main Results:

  • MPWN evaluated on Fashion-MNIST and CIFAR10 datasets.
  • Achieved efficient search for optimal weight space combinations using the accuracy sparsity bit score.
  • XOR signed-bits and ternary bitwise operations provide efficient hardware implementations.
  • MPWN implementation on FPGA used 1.68-4.89 times fewer hardware resources than 32-bit models.
  • MPWN implementation reduced latency by up to 31.55 times compared to unoptimized 32-bit models.

Conclusions:

  • The mixed-precision weights network (MPWN) offers significant hardware resource and latency advantages.
  • MPWN demonstrates effective integration of diverse weight precision levels for enhanced efficiency.
  • The proposed software and hardware optimizations facilitate practical deployment of MPWN on FPGAs.