High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded...

Area of Science:

• Computer Engineering
• Cybersecurity
• Embedded Systems

Background:

• Embedded Systems-on-Chip (SoCs) face security vulnerabilities in main memory data exchanges, risking data leakage and execution failures.
• Safety-critical applications demand robust protection against external attacks like bus monitoring and data tampering.

Purpose of the Study:

• To present a novel security SoC architecture integrating a high-efficiency cryptographic accelerator.
• To ensure secure data exchange between SoCs and main memory against various threats.

Main Methods:

• Designed and implemented a security SoC architecture featuring a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator.
• Verified the design on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform.
• Evaluated performance overhead, security, processing efficiency, and resource consumption.

Main Results:

• The parallel AES-GCM accelerator provides confidentiality and integrity with an average performance overhead as low as 2.65% on 8-KB I/D-Caches.
• Achieved approximately 3 times the data processing efficiency compared to pipelined AES-GCM constructions.
• Demonstrated effectiveness against data tampering attacks and external physical threats.

Conclusions:

• The enhanced SoC architecture offers a strong balance between high-efficiency data processing and hardware overhead.
• The integrated cryptographic accelerator significantly improves data exchange security in embedded systems without substantial performance penalties.
• The solution is effective against external physical attacks, ensuring data integrity and confidentiality.