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Cruise control systems in cars are designed as multi-input systems to maintain a driver's desired speed while compensating for external disturbances such as changes in terrain. The block diagram for a cruise control system typically includes two main inputs: the desired speed set by the driver and any external disturbances, such as the incline of the road. By adjusting the engine throttle, the system maintains the vehicle's speed as close to the desired value as possible.
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Complexity Analysis of a Versatile Video Coding Decoder over Embedded Systems and General Purpose Processors.

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Summary

This study profiles the Versatile Video Coding (VVC) decoder on different processors, identifying computationally intensive modules for future acceleration. Understanding hardware architecture influence is key for optimizing VVC performance.

Keywords:
H.266adaptive loop filtercodeccomplexity analysisdeblocking filterheterogeneous, GPUinter predictionmulticoreversatile video coding

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Area of Science:

  • Computer Science
  • Electrical Engineering
  • Signal Processing

Background:

  • High-quality video consumption drives demand for efficient video coding.
  • Versatile Video Coding (VVC) is the latest standard, offering ~50% better compression than HEVC but with higher complexity.
  • Profiling VVC decoders is crucial for performance optimization.

Purpose of the Study:

  • To perform coarse-grain and fine-grain profiling of a VVC decoder.
  • To identify computationally intensive modules within the VVC decoder.
  • To analyze the influence of hardware architecture on VVC decoder performance across different platforms.

Main Methods:

  • Coarse-grain profiling of a VVC decoder on a High-Performance General Purpose Processor (HGPP) and an Embedded General Purpose Processor (EGPP).
  • Fine-grain profiling of the most computationally intensive modules.
  • Correlation analysis of module performance across different hardware platforms.

Main Results:

  • Identification of the most computationally demanding modules in the VVC decoder.
  • Quantification of performance differences between HGPP and EGPP platforms.
  • Determination of the correlation between module performance and hardware architecture.

Conclusions:

  • Profiling identified key modules for targeted acceleration efforts.
  • Hardware architecture significantly influences VVC decoder performance.
  • Results provide a foundation for optimizing VVC implementation on diverse platforms.