On-CMOS Image Sensor Processing for Lane Detection.

Area of Science:

• Integrated Circuits
• Computer Vision
• Automotive Engineering

Background:

• Lane detection is crucial for advanced driver-assistance systems (ADAS).
• Existing methods often require significant off-chip processing, increasing latency and power consumption.
• Need for efficient, integrated solutions for real-time automotive applications.

Purpose of the Study:

• To develop a CMOS image sensor (CIS) with integrated lane detection capabilities.
• To enhance lane detection accuracy, particularly for slanting lanes.
• To achieve high-speed processing and low power consumption for automotive applications.

Main Methods:

• On-chip processing using an edge detection mask integrated into the readout circuit of a conventional CIS.
• Fabrication of a prototype CIS using a 110 nm CMOS process.
• Evaluation of lane detection accuracy against existing algorithms.

Main Results:

• The prototype CIS achieved an image resolution of 160x120 pixels and a frame rate of 113 fps.
• The integrated edge detection mask demonstrated acceptable accuracy in detecting slanting lanes.
• The total power consumption was measured at 9.7 mW.

Conclusions:

• The proposed on-CIS lane detection technology offers a viable solution for high-speed and accurate automotive lane detection.
• Integration of processing directly onto the sensor reduces power consumption and improves efficiency.
• The developed edge detection mask effectively handles challenging lane scenarios, improving ADAS performance.