A graph placement methodology for fast chip design.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Machine Learning

Background:

• Chip floorplanning, the physical layout design of computer chips, has historically required extensive manual effort from engineers.
• Despite decades of research, automating this complex process has remained a significant challenge in the field.

Purpose of the Study:

• To develop an automated solution for chip floorplanning using artificial intelligence.
• To create a deep reinforcement learning approach that surpasses human performance in chip layout design.

Main Methods:

• Formulated chip floorplanning as a reinforcement learning problem.
• Developed an edge-based graph convolutional neural network architecture for learning chip representations.
• Trained the AI model using past design experiences for continuous improvement.

Main Results:

• The AI method generated chip floorplans in under six hours, significantly faster than traditional methods.
• The automatically generated layouts were superior or comparable to human-designed layouts across key metrics like power, performance, and area.
• The AI model demonstrated improved efficiency and speed on new chip design instances due to its learning capabilities.

Conclusions:

• The deep reinforcement learning approach offers a viable and highly efficient solution for automated chip floorplanning.
• This AI-driven method has the potential to save thousands of engineering hours per chip generation and accelerate AI hardware development.
• The advancement fosters a symbiotic relationship between AI and hardware design, driving mutual progress in both fields.