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Summary
This summary is machine-generated.

This study presents an asynchronous, clockless readout circuit for single-photon avalanche diode (SPAD) arrays, significantly improving energy efficiency and data rates for applications like medical imaging and optical communications.

Keywords:
SPADasynchronous logicfixed priority arbitermicropipelinereadout

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Area of Science:

  • Photonics and Microelectronics Engineering
  • Digital Circuit Design

Background:

  • Single-photon avalanche diode (SPAD) arrays are crucial for advanced imaging and communication systems.
  • Traditional synchronous readout circuits face limitations in energy consumption and data rate due to clocking requirements.
  • Asynchronous (clockless) logic offers a promising alternative to overcome these limitations.

Purpose of the Study:

  • To design and validate an asynchronous readout circuit for SPAD arrays.
  • To address the challenges of reducing energy consumption and increasing data rates in SPAD array systems.
  • To demonstrate the feasibility of clockless logic for high-performance SPAD applications.

Main Methods:

  • Design of a 16-to-1 fixed-priority tree arbiter readout circuit utilizing asynchronous logic principles.
  • Detailed explanation of the circuit design, supported by simulation results.
  • Fabrication and experimental testing of the designed chip.

Main Results:

  • The asynchronous readout circuit achieved a high event recording rate of up to 333 million events per second.
  • No reading errors were detected during data extraction tests, confirming the reliability of the design.
  • The clockless approach demonstrated superior performance compared to conventional synchronous designs.

Conclusions:

  • Asynchronous logic is a viable and effective alternative for designing SPAD array readout circuits.
  • The developed circuit offers significant improvements in energy efficiency and data throughput.
  • This work paves the way for more advanced and efficient SPAD-based systems in various fields.