Neural Network Training Acceleration With RRAM-Based Hybrid Synapses.

Area of Science:

• Materials Science and Engineering
• Computer Engineering
• Artificial Intelligence

Background:

• Hardware neural networks (HNNs) leverage analog synapse arrays for accelerated parallel computation.
• Energy-efficient and accurate HNNs require high-precision synaptic devices and fully-parallel operations.
• Existing resistive memory (RRAM) devices have limited conductance states, hindering HNN performance.

Purpose of the Study:

• To propose a novel RRAM-based hybrid synaptic unit for energy-efficient HNNs.
• To enable array-wise fully-parallel learning with RRAM synaptic units.
• To overcome the limitations of finite conductance states in RRAM devices for HNN applications.

Main Methods:

• Developed a hybrid synaptic unit comprising a "big" and a "small" RRAM synapse.
• Implemented a training method compatible with the proposed hybrid architecture for parallel learning.
• Utilized Mo/TiO_x RRAM devices, exploiting areal dependency of conductance precision.
• Conducted neural network simulations to evaluate accuracy and efficiency.

Main Results:

• The proposed hybrid synapse architecture enables array-wise fully-parallel learning with simple array selection logic.
• Mo/TiO_x RRAM devices demonstrated tunable conductance precision through proportional scaling of device area.
• RRAM-based hybrid synapses achieved 97% accuracy in simulations, closely matching software floating-point implementations (97.92%).
• The system achieved high accuracy despite using devices with only 50 discrete conductance states.

Conclusions:

• The RRAM-based hybrid synaptic unit offers a viable solution for energy-efficient and high-accuracy HNNs.
• The proposed architecture and training method facilitate efficient parallel learning, overcoming RRAM limitations.
• This work paves the way for improved training efficiency and inference accuracy in RRAM-based HNNs.