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A pseudo-softmax function for hardware-based high speed image classification.

Gian Carlo Cardarilli1, Luca Di Nunzio1, Rocco Fazzolari1

  • 1Department of Electronic Engineering, University of Rome "Tor Vergata", 00133, Rome, Italy.

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Summary
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A new pseudo-softmax architecture approximates the softmax function for efficient hardware implementation in neural networks. This novel design reduces approximation errors in classification and reinforcement learning tasks.

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Area of Science:

  • Computer Science
  • Electrical Engineering
  • Artificial Intelligence

Background:

  • The softmax function is crucial for classification and reinforcement learning but computationally intensive.
  • Hardware implementations of neural networks often use integer quantization, which can affect function accuracy.

Purpose of the Study:

  • To introduce a novel pseudo-softmax architecture for efficient hardware implementation.
  • To achieve accurate approximation of the softmax function using integer quantization.
  • To reduce approximation errors in neural network and reinforcement learning applications.

Main Methods:

  • Development of a novel pseudo-softmax hardware architecture.
  • Analysis of approximation errors using custom stimuli and real-world Convolutional Neural Networks (CNNs) data.
  • Implementation using standard-cell CMOS technology.

Main Results:

  • The pseudo-softmax architecture provides an accurate approximation of the softmax function.
  • Hardware implementation demonstrates reduced approximation errors compared to state-of-the-art methods.
  • The design is suitable for efficient hardware acceleration in neural networks and reinforcement learning.

Conclusions:

  • The proposed pseudo-softmax architecture offers an efficient and accurate hardware solution for approximating the softmax function.
  • This innovation is beneficial for resource-constrained hardware accelerators in deep learning and reinforcement learning.
  • The study validates the effectiveness of the pseudo-softmax design through rigorous error analysis and implementation.