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Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory.

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This study introduces a novel neural network-assisted error correction scheme for multi-level cell NAND flash memory. The ANNAEC method enhances data reliability and NAND flash memory endurance by addressing multiple noise sources.

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Area of Science:

  • Electrical Engineering
  • Computer Science

Background:

  • NAND flash memory scaling improves storage density but degrades data reliability due to noise.
  • Existing noise mitigation technologies address only single noise sources, limiting effectiveness.

Purpose of the Study:

  • To propose a novel neural network-assisted error correction (ANNAEC) scheme for multi-level cell (MLC) NAND flash memory.
  • To enhance data reliability and endurance by mitigating multiple noise sources in NAND flash memory channels.

Main Methods:

  • Developed a neural network-assisted error correction (ANNAEC) scheme.
  • Proposed a relative log-likelihood ratio (LLR) to estimate actual LLR, avoiding retention time as an input.
  • Transformed bit detection into a clustering problem, using a neural network to learn NAND flash memory channel error characteristics.

Main Results:

  • The ANNAEC scheme effectively mitigates multiple noise sources in MLC NAND flash memory.
  • The proposed relative LLR method accurately estimates LLR without retention time data.
  • Trained neural network optimized bit error detection performance.

Conclusions:

  • The ANNAEC scheme significantly improves bit error detection performance in MLC NAND flash memory.
  • The proposed method enhances the overall endurance of NAND flash memory devices.
  • This approach offers a comprehensive solution for data reliability challenges in advanced NAND flash memory.