Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness.

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Traditional chip interconnection methods require time-consuming and expensive surface nanoscopic planarization.
• Existing bonding techniques often necessitate intermediate conductive materials, adding complexity and cost.

Purpose of the Study:

• To explore a new method for simultaneous mechanical, thermal, and electrical connections between metallic surfaces.
• To demonstrate a technique that bypasses the need for surface nanoscopic planarization and intermediate conductive materials.
• To apply the novel method for attaching high-power Gallium Nitride (GaN)-based semiconductor dies.

Main Methods:

• Utilizing intrinsic nanoscopic surface roughness for interlocking surfaces.
• Employing a conventional die bonder for electrical interconnection and bonding.
• Stabilizing the connection with a dielectric adhesive filling nanoscale valleys, termed "nano-locking" (NL).

Main Results:

• Achieved a bond-line thickness under 100 nm, significantly thinner than mainstream methods.
• Demonstrated reduced overall device thermal and electrical resistance due to the thin bond-line.
• Showcased improved overall device performance and reliability in GaN-based devices.

Conclusions:

• The nano-locking (NL) method provides a scalable, reliable, and simple approach for nanoscale off-chip electrical interconnection and bonding.
• The bond-line thickness critically influences contact area, contact resistance, and consequently, device performance and reliability.
• The NL method is applicable to bonding any surfaces with intrinsic or engineered nanoscopic structures.