FPGA-Based Processor Acceleration for Image Processing Applications.

Area of Science:

• Embedded Systems
• Computer Vision
• Hardware Acceleration

Background:

• FPGA-based embedded systems provide substantial computational power but are difficult to program.
• Existing solutions often require complex hardware description languages or lack efficient programming models.

Purpose of the Study:

• To present a novel FPGA-based soft processor, the Image Processing Processor (IPPro), designed to simplify embedded image processing.
• To demonstrate the effectiveness of IPPro through k-means clustering and traffic sign recognition applications.
• To evaluate the performance and power efficiency of IPPro compared to traditional software implementations.

Main Methods:

• Development of the Image Processing Processor (IPPro), an FPGA-based soft processor capable of operating at 337 MHz.
• Implementation of a dataflow-based programming environment tailored for IPPro.
• Prototyping of k-means clustering and traffic sign recognition on an Avnet Zedboard with Xilinx Zynq-7000 SoC.
• Exploration of parallel dataflow mapping strategies.

Main Results:

• Achieved an 8x speed-up for k-means clustering and a 9.6x speed-up for a morphology filter in traffic sign recognition using 16 IPPro cores compared to ARM software.
• Demonstrated superior power efficiency for k-means clustering with 16 IPPro cores, being 57x, 28x, and 1.7x more efficient than ARM Cortex-A7 CPU, NVIDIA GeForce GTX980 GPU, and ARM Mali-T628 GPU, respectively.

Conclusions:

• The IPPro approach effectively addresses the programming challenges of FPGA-based embedded image processing.
• IPPro offers significant performance gains and power efficiency improvements for demanding image processing tasks.
• This methodology enables high-performance, power-efficient embedded vision systems on FPGAs.