One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors.

Area of Science:

• Semiconductor device physics
• Solid-state electronics
• Memory technology

Background:

• Static random-access memory (SRAM) is crucial for modern electronics.
• Developing low-power, high-performance memory cells remains a key challenge.
• One-transistor (1T) SRAM architectures offer potential for reduced cell size and power consumption.

Purpose of the Study:

• To fabricate and characterize a 2x2 array of single-gated feedback field-effect transistor (FET) based 1T-SRAM cells.
• To evaluate the operational and memory characteristics of the fabricated 1T-SRAM cells.
• To assess the reliability and disturbance immunity of the 1T-SRAM cell array.

Main Methods:

• Fabrication of a 2x2 1T-SRAM cell array using single-gated feedback FETs.
• Experimental measurement of individual cell retention time, nondestructive read characteristics, and endurance.
• Estimation of standby power consumption for both '0' and '1' states.
• Testing of nondestructive reading in a selected cell within the array without disturbing half-selected cells.

Main Results:

• Individual 1T-SRAM cells exhibited a retention time exceeding 900 seconds and nondestructive reading capabilities for up to 10,000 seconds.
• The cells demonstrated high endurance, reaching 10^8 cycles.
• Standby power was remarkably low: 0.7 pW for the '0' state and 6 nW for the '1' state.
• Nondestructive reading of a selected cell was achieved without disturbing half-selected cells in the 2x2 array.

Conclusions:

• The fabricated single-gated feedback FET based 1T-SRAM cells show promising memory characteristics, including long retention and nondestructive readouts.
• The low standby power consumption makes this 1T-SRAM architecture suitable for energy-efficient applications.
• The demonstrated immunity to disturbances in the array validates the reliability of this 1T-SRAM cell design for practical implementation.