An FPGA-based design for power efficient low delay rate adaptive pacemaker using accelerometer and heart rate sensor.

Area of Science:

• Biomedical Engineering
• Implantable Medical Devices
• Digital Health

Background:

• Pacemaker design modifications are ongoing, but open-source implantable device development remains a challenge.
• Bradycardia patients require pacemakers to regulate heart rate, with efficiency and responsiveness being critical parameters.
• Existing pacemaker designs may face limitations in power consumption and response delay.

Purpose of the Study:

• To propose a proof of concept for a power-efficient, low-delay, rate-adaptive dual chamber pacemaker (PLRDPM) on an FPGA platform.
• To enhance vital parameters such as delay and power consumption in pacemaker functionality.
• To leverage sensor data for a more responsive and efficient pacing algorithm.

Main Methods:

• Development of a dual chamber pacemaker (PLRDPM) on an FPGA.
• Integration of heart rate and accelerometer sensors to monitor physical activity and its effect on heart rate.
• Design of a rate-adaptive pacing algorithm utilizing data from both sensors.

Main Results:

• Achieved a power consumption of 9 mW.
• Attained a low circuit delay of 2.82 ns.
• Demonstrated a functional proof of concept for the PLRDPM design.

Conclusions:

• The proposed PLRDPM design on FPGA offers significant improvements in power efficiency and delay reduction.
• The rate-adaptive algorithm effectively utilizes sensor data for optimized bradycardia patient care.
• This open-source approach provides a foundation for future advancements in implantable pacemaker technology.