Neural-Network Based Modeling of I/O Buffer Predriver under Power/Ground Supply Voltage Variations.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Semiconductor Device Physics

Background:

• Nonlinear switching behavior in I/O buffers causes timing distortion.
• Power and ground supply voltage (PGSV) variations significantly impact buffer performance.
• Existing behavioral models may not fully capture these nonlinear dynamics.

Purpose of the Study:

• To develop a neural-network based nonlinear behavioral model for I/O buffers.
• To accurately account for timing distortion caused by predriver circuit nonlinearities under PGSV variations.
• To improve the accuracy of electronic circuit simulations.

Main Methods:

• Modeling the I/O buffer's last stage using nonlinear current-voltage (I-V) and capacitance-voltage (C-V) functions.
• Deriving a mathematical model for the predriver from large-signal switching behavior analysis.
• Utilizing a multilayer neural network (NN) trained on timing series data reflecting PGSV variations.
• Implementing the NN model in a time-domain solver.

Main Results:

• The proposed NN model accurately captures nonlinear dynamic impedances of transistors.
• Validation against transistor-level (TL) and IBIS models demonstrated superior performance under various scenarios.
• Jitter analysis using eye diagrams confirmed the model's effectiveness in predicting timing distortions.

Conclusions:

• The neural-network based model provides a robust solution for predicting I/O buffer timing distortion.
• This approach enhances the accuracy of behavioral modeling for electronic circuits, especially under voltage fluctuations.
• The validated model offers a valuable tool for designers dealing with signal integrity issues.