Recurrent neural network FPGA hardware accelerator for delay-tolerant indoor optical wireless communications

Area of Science:

• Optical Wireless Communication (OWC)
• Machine Learning for Communications
• Hardware Acceleration

Background:

• Optical wireless communication (OWC) is crucial for high-speed indoor applications.
• Transmitter diversity in OWC is susceptible to channel delays.
• Existing neural network solutions like LSTM and ALSTM offer delay tolerance but have high computational costs.

Purpose of the Study:

• To propose a low-complexity, delay-tolerant recurrent neural network (RNN) scheme for indoor OWC systems.
• To develop and demonstrate a Field-Programmable Gate Array (FPGA)-based RNN hardware accelerator for practical OWC systems.
• To optimize the hardware accelerator for reduced processing latency and power consumption.

Main Methods:

• Developed a parallelized RNN structure to decrease computation cost.
• Implemented a Field-Programmable Gate Array (FPGA)-based hardware accelerator for the proposed RNN.
• Introduced parallel implementation with triple-phase clocking and stream-in computation for optimization.

Main Results:

• Achieved bit-error-rate (BER) performance within the forward-error-correction (FEC) limit for delays up to 5.5 symbol periods.
• The FPGA-based accelerator with optimizations reduced latency by 96.75% and energy consumption by 90.7% compared to unoptimized versions.
• Compared to GPU implementations, the FPGA solution reduced latency by approximately 61% and power consumption by 58.1%.

Conclusions:

• The proposed low-complexity RNN scheme effectively addresses delay tolerance in indoor OWC systems.
• The FPGA-based hardware accelerator provides a practical, efficient solution for delay-tolerant OWC.
• Optimization techniques significantly enhance the performance of the FPGA accelerator, making it superior to GPU implementations for OWC applications.