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A schema is a mental framework that helps individuals organize and interpret information. Schemata, formed from previous experiences, influence how we process new information: how we encode it, the inferences we make, and how we retrieve it. For instance, a schema for what a typical classroom looks like might include desks, a teacher's desk, a whiteboard, and students in such an environment. This expectation helps us quickly understand and navigate new classrooms without needing to analyze...
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RRAM-based CAM combined with time-domain circuits for hyperdimensional computing.

Yasmin Halawani1, Dima Kilani1, Eman Hassan1

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Summary
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This study introduces an XNOR-based Resistive RAM Content Addressable Memory (RRAM-CAM) for faster, lower-power AI tasks. The novel design significantly reduces area and energy consumption compared to traditional methods.

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Area of Science:

  • Utilizes in-memory computing with Resistive RAM (RRAM) for efficient Content Addressable Memory (CAM) applications.
  • Focuses on hardware acceleration for artificial intelligence (AI) tasks, particularly on resource-constrained platforms.

Background:

  • Content addressable memory (CAM) is crucial for high-speed search and match operations in critical domains, demanding low power consumption.
  • Resistive RAM (RRAM)-based in-memory computing offers a promising approach for efficient static CAM, especially for AI workloads.

Purpose of the Study:

  • To present an XNOR-based RRAM-CAM integrated with a time-domain analog adder for efficient winning class computation.
  • To demonstrate the effectiveness of the proposed design for hyperdimensional computing in MNIST classification.

Main Methods:

  • Developed an XNOR-based RRAM-CAM that compares voltage and resistance operands to output similarity voltages.
  • Employed time-domain analog addition to process similarity voltages, mitigating issues like voltage saturation, variation, and noise.
  • Utilized a digital realization to identify the winning class based on the longest pulse width.

Main Results:

  • The proposed RRAM-CAM design, implemented using 65 nm CMOS technology, achieved a total area of 0.0077 mm².
  • Demonstrated low energy consumption of 13.6 pJ per 1k query within a 10 ns clock cycle.
  • Achieved significant reductions in area (~31x) and energy consumption (~3x) compared to fully digital ASIC implementations.

Conclusions:

  • The XNOR-based RRAM-CAM with a time-domain analog adder offers a highly efficient solution for AI tasks.
  • The design presents a remarkable reduction in area and energy consumption compared to existing state-of-the-art RRAM designs.
  • This approach is particularly beneficial for resource-constrained platforms requiring near real-time decision-making.