A Low-Power DNN Accelerator Enabled by a Novel Staircase RRAM Array.

Area of Science:

• Computer Engineering
• Materials Science
• Artificial Intelligence

Background:

• The Internet of Things (IoT) requires efficient deep neural network (DNN) accelerators for ubiquitous sensors and connected devices.
• Existing accelerators face challenges in power consumption, size, and computational efficiency.
• Emerging memory technologies offer potential for low-power, compact hardware solutions.

Purpose of the Study:

• To design a hardware-aware DNN accelerator that enhances power and area efficiency.
• To leverage analog in-memory computing with resistive random-access memory (RRAM) for reduced energy consumption.
• To develop a variation-tolerant in-memory compute methodology for robust performance.

Main Methods:

• Integration of a planar-staircase RRAM array with an in-memory compute methodology.
• Utilizing pulse application at bottom electrodes for concurrent input shift, eliminating unfolding and regeneration.
• Employing a charge-domain in-memory compute approach for high-accuracy floating-point operations.

Main Results:

• Achieved a 5.64× enhancement in peak power efficiency compared to state-of-the-art DNN accelerators.
• Demonstrated a 4.7× improvement in area efficiency.
• Facilitated high-accuracy floating-point computations using low RRAM states with minimal device requirements.

Conclusions:

• The developed RRAM-based DNN accelerator offers a significant advancement in energy and area efficiency.
• This design provides a viable path toward fast, low-power, and compact hardware accelerators for IoT.
• The in-memory compute methodology enables efficient deep learning computations on resource-constrained devices.