Modeling of Statistical Variation Effects on DRAM Sense Amplifier Offset Voltage

Area of Science:

• Semiconductor device physics
• Integrated circuit reliability
• Memory technology

Background:

• Device downscaling intensifies process-induced parameter variations.
• Variations in dynamic random-access memory (DRAM) sense amplifiers lead to offset voltage and sensing failures.
• Threshold voltage mismatch in sense amplifier transistors is a critical factor.

Purpose of the Study:

• To numerically investigate the prediction accuracy and reliability of offset voltage in DRAM wafers.
• To introduce virtual wafer generation with statistical threshold voltage (V_T) variation.
• To enhance in-line wafer controllability for securing DRAM sensing margin.

Main Methods:

• Generation of virtual wafers incorporating statistical V_T variation.
• Numerical investigation of offset voltage prediction accuracy and reliability.
• Utilizing test point measurements for validation.

Main Results:

• Demonstrated the accuracy and reliability of offset voltage prediction using virtual wafers.
• Quantified the impact of V_T variation on DRAM sensing performance.
• Established a novel method for assessing wafer-level variations.

Conclusions:

• The proposed virtual wafer approach effectively predicts DRAM offset voltage.
• This method enhances in-line controllability, crucial for maintaining DRAM sensing margins.
• The study provides a pathway to mitigate sensing failures caused by parameter variations.