Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications

Area of Science:

• Computer Engineering
• VLSI Design
• Parallel Computing

Background:

• Network-on-Chip (NoC) is crucial for intra-chip communication.
• Irregular topologies offer application-specific advantages over regular ones.
• Optimizing NoC design requires thorough design space exploration.

Purpose of the Study:

• To optimize irregular Network-on-Chip topologies using a genetic algorithm.
• To enhance support for real-time tasks within heterogeneous networks.
• To minimize average latency and maximize real-time packet delivery.

Main Methods:

• Utilized a genetic algorithm for design space exploration of NoC topologies.
• Introduced heterogeneous routers to optimize network performance.
• Focused on optimizing for average latency and real-time packet deadline adherence.

Main Results:

• Successfully identified optimized irregular topologies.
• Achieved delivery of all real-time packets within their deadlines.
• Demonstrated acceptable average latency values.
• Reported a reduction in overall chip area.

Conclusions:

• Genetic algorithms are effective for optimizing irregular NoC topologies.
• Heterogeneous routers enhance NoC performance for real-time applications.
• The proposed method balances latency, real-time guarantees, and area efficiency.