A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator.

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Signal Processing

Background:

• Sampling-based Phase-Locked Loops (PLLs) offer noise reduction by removing frequency dividers (FDIVs).
• Reference-sampling provides a wider locking range compared to sub-sampling.
• Implementing fractional-N operation without FDIVs presents a design challenge.

Purpose of the Study:

• To propose a novel reference-sampling-based calibration-free fractional-N PLL (RSFPLL).
• To enable fractional-N operation without a traditional frequency divider.
• To address design challenges in sampling-based PLLs.

Main Methods:

• Utilized a phase-interpolator-linked sampling clock generator (PSCG) for fractional-N operation.
• Employed phase-interpolator (PI)-based multi-phase generation instead of a frequency divider or digital-to-time converter (DTC).
• Implemented a flexible mask window generation method to reduce power consumption.

Main Results:

• Achieved 322 fs root-mean-square (rms) jitter.
• Attained a figure-of-merit (FoM) of -240.7 dB.
• Suppressed fractional spurs to -44.06 dBc.
• Consumed 8.17 mW power.

Conclusions:

• The proposed RSFPLL successfully integrates fractional-N capabilities into a reference-sampling PLL architecture.
• The design demonstrates a viable method for achieving high performance and low power consumption in PLLs.
• This work advances the field of sampling-based PLLs for improved noise and spur performance.