Nonvolatile Logic and Ternary Content-Addressable Memory Based on Complementary Black Phosphorus and Rhenium Disulfide Transistors

Hardware realization of in-memory computing for efficient data-intensive computation is regarded as a promising paradigm beyond the Moore era. However, to realize such functions, the device structure using traditional Si complementary metal-oxide-semiconductor (CMOS) technology is complex with a large footprint. 2D material-based heterostructures have a unique advantage to build versatile logic functions based on novel heterostructures with simplified device footprint and low power. Here, by adopting the charge-trapping mechanism between a black phosphorus (BP) channel and a phosphorus oxide (PO_x ) layer, a nonvolatile CMOS logic circuit based on 2D BP and rhenium disulfide (ReS₂ ) with a high voltage gain of ≈275 is realized with a persistent hysteresis window. A Schmidt-like flip-flop using only two transistors is also demonstrated, with far fewer transistor numbers than the conventional silicon counterpart, which usually requires six transistors. Furthermore, four-transistor (4T) nonvolatile ternary content-addressable memory (nvTCAM) cells are demonstrated with far fewer transistors for parallel data search. The nvTCAM cells exhibit high resistance ratios (R_ratio ) up to ≈10³ between match and mismatch states with zero standby power thanks to the nonvolatility of the BP transistors. This back-end-of-line compatible nvTCAM shows advantages over other structures with reduced complexity and thermal budget.