Monolithic Three-Dimensional Tuning of an Atomically Defined Silicon Tunnel Junction

Area of Science:

• Quantum computing
• Solid-state physics
• Nanotechnology

Background:

• Quantum information processors require tunable tunnel rates and exchange interactions.
• Atom qubits in silicon offer large energy level separation but limited tunability with in-plane gates.
• Vertically separated top-gates are needed to control tunneling in such devices.

Purpose of the Study:

• To demonstrate precise control over the simplest tunneling device in silicon: phosphorus (Si:P) tunnel junctions.
• To investigate the efficacy of vertically separated top-gates for tuning device conductance.
• To explore the implementation of nanoscale logic circuits using this gating technology.

Main Methods:

• Fabrication of a monolithic 3D epitaxial top-gate structure precisely aligned to Si:P tunnel junctions (±5 nm precision).
• Measurement of the tunnel junction conductance as a function of gate voltage.
• Characterization of tunnel barrier height tunability.
• Integration of multiple gated junctions to form nanoscale logic gates (AND, OR).

Main Results:

• Demonstrated precise tuning of tunnel junction conductance using the vertically separated top-gate.
• Showcased a threefold increase in capacitive coupling compared to in-plane gates.
• Achieved a wide tunnel barrier height tunability range of 0-186 meV.
• Successfully implemented nanoscale AND and OR logic gates by combining multiple gated junctions.

Conclusions:

• Monolithic 3D epitaxial top-gate technology offers superior capacitive coupling for enhanced control over Si:P tunnel junctions.
• This approach significantly improves device tunability, a critical requirement for quantum information processors.
• The developed gating technology provides a viable pathway for building complex nanoscale logic circuits for quantum applications.