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Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory.
Woo-Jin Jung1, Jun-Young Park1
1School of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Chungbuk, Cheongju 28644, Korea.
Micromachines
|November 27, 2021
Summary
Controlling cell-to-cell interference in 3D NAND flash memory is challenging due to increased word-lines (WLs). This study explores dielectric engineering and proposes a new cell structure to mitigate voltage interference in 3D NAND devices.
Area of Science:
- Materials Science
- Electrical Engineering
- Semiconductor Physics
Background:
- 3D NAND flash memory offers higher storage density than 2D NAND.
- Increased word-line (WL) count in 3D NAND exacerbates cell-to-cell interference due to parasitic capacitance.
- Existing methods struggle to control this interference within limited vertical space.
Purpose of the Study:
- To investigate voltage interference characteristics in 3D NAND flash memory concerning dielectric materials.
- To propose an innovative cell structure for suppressing cell-to-cell interference.
- To enhance the reliability and performance of 3D NAND devices.
Main Methods:
- Analysis of parasitic capacitance effects between WLs in 3D NAND structures.
- Simulation and characterization of dielectric properties influencing voltage interference.
- Design and conceptualization of an alternative 3D NAND cell architecture.
Main Results:
- Identified key dielectric properties that significantly impact WL-to-WL interference.
- Demonstrated the potential of dielectric engineering to reduce parasitic capacitance.
- Proposed a novel cell structure exhibiting suppressed voltage interference.
Conclusions:
- Dielectric engineering is a viable strategy for managing interference in 3D NAND.
- The proposed cell structure effectively mitigates voltage interference, improving device performance.
- Further research into advanced dielectric materials and cell designs is warranted for next-generation 3D NAND.
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