Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Convolutional Neural Networks (CNNs) demand substantial memory access, leading to high energy consumption, especially with increasing network scale.
• Data migration between on-chip buffers and off-chip DRAM significantly contributes to energy usage, often exceeding computation energy.
• Inefficient hardware utilization arises from static configurations that do not adapt to varying layer dimensions in CNNs.

Purpose of the Study:

• To develop a methodology for optimizing CNN hardware configurations layer by layer.
• To reduce energy consumption associated with memory access and data migration in CNNs.
• To provide guidance for efficient hardware resource utilization in CNN accelerators.

Main Methods:

• Proposing a methodology to adapt Processing Element (PE) array architecture, buffer assignment, dataflow, and reuse strategies.
• Layer-by-layer configuration adaptation based on CNN architecture and hardware resources.
• Exploring combinations of configuration issues to assess effectiveness.

Main Results:

• A quick and efficient methodology for adapting CNN hardware configurations is presented.
• The approach aims to maximize data reuse and minimize data migration.
• The study explores configuration combinations to guide optimization processes.

Conclusions:

• The proposed methodology enables efficient, layer-specific hardware configuration for CNNs.
• Optimized dataflows and configurations significantly reduce energy consumption from memory access.
• This work provides a framework for accelerating the exploration of optimal CNN hardware designs.