A dual mode self-test for a stand alone AES core.

Area of Science:

• Computer Engineering
• Cybersecurity
• Integrated Circuit Design

Background:

• Advanced Encryption Standard (AES) is a highly secure symmetric encryption algorithm, with hardware implementations offering superior speed and physical security over software.
• AES chips face challenges in testability and vulnerability to hardware Trojans, which can compromise security by leaking information.

Purpose of the Study:

• To address the unaddressed problem of testability in complex AES chips.
• To propose a novel dual-mode self-test architecture for detecting hardware Trojans and parametric chip defects.

Main Methods:

• Partitioning the AES circuit into smaller, self-referencing blocks.
• Implementing a comparative power ratio threshold for enhanced detection accuracy.
• Utilizing built-in current sensors and considering process variations for threshold determination.

Main Results:

• The proposed architecture effectively detects hardware Trojans during manufacturing tests.
• It enables online parametric testing to identify chip defects.
• Achieves reduced delay, power consumption, and area overhead compared to existing methods.

Conclusions:

• The dual-mode self-test architecture significantly improves the security and testability of AES hardware.
• It offers a practical solution for identifying malicious hardware insertions and manufacturing defects.
• This approach contributes to more robust and secure integrated circuits.