Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs

Area of Science:

• Electrical Engineering
• Computer Architecture
• Nanotechnology

Background:

• Adders are crucial components in arithmetic circuits for computation.
• Approximate computing is an emerging field focused on energy-efficient, high-performance circuits.
• Carbon nanotube field-effect transistor (CNFET) technology offers potential for advanced circuit design.

Purpose of the Study:

• To present novel 10T and 13T approximate adder (AA) designs utilizing CNFET technology.
• To evaluate the performance of these AA designs against existing circuits.
• To demonstrate the energy efficiency and accuracy improvements offered by the proposed designs.

Main Methods:

• Designs for 10T and 13T approximate adders were developed using CNFET technology.
• Simulations were performed using the HSPICE tool with 32 nm CNFET technology.
• Key performance metrics including average power, power-delay product (PDP), energy delay product (EDP), and propagation delay were analyzed at a supply voltage of 0.9 V.

Main Results:

• The proposed 10T and 13T CNFET approximate adders demonstrated reduced power consumption compared to existing designs.
• The power-delay product (PDP) and energy delay product (EDP) were significantly minimized.
• The designs achieved a favorable balance between accuracy and performance metrics.

Conclusions:

• The presented 10T and 13T CNFET approximate adders offer a promising solution for energy-efficient computation.
• These designs provide lower PDP and power consumption with competitive accuracy.
• CNFET technology is well-suited for developing high-performance, low-power approximate adders.