Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology

Area of Science:

• Integrated circuit design
• Biomedical engineering
• Low-power electronics

Background:

• Miniaturized, ultra-low power interfaces are critical for energy-constrained health monitoring applications like wearable, ingestible, and implantable devices.
• Capacitive sensors and their digital readout interfaces are essential components in these systems.

Purpose of the Study:

• To analyze and design a novel capacitance-to-digital converter (CDC) utilizing an iterative delay-chain discharge architecture.
• To demonstrate the circuit's operating principles, design trade-offs, and performance in a practical application.

Main Methods:

• Design and simulation of a CDC in a 180 nm CMOS process.
• Utilizing an iterative delay-chain discharge architecture for capacitance-to-digital conversion.
• Testing the design across various process and temperature corners (-40 °C to +125 °C).

Main Results:

• Achieved ultra-low energy consumption (≤1.884 nJ/conversion) and excellent linearity (15.26 ppm error).
• Demonstrated good robustness against process variations (114.0 ppm sensitivity) and temperature fluctuations (81.9 ppm/°C).
• The circuit occupies a small silicon area (0.0192 mm²) and has a conversion time of 2.93 ms, with a resolution of 10.3 effective bits.

Conclusions:

• The designed CDC is suitable for ultra-low power, miniaturized sensor interfaces in medical and health applications.
• The iterative delay-chain discharge architecture offers a promising approach for efficient capacitance-to-digital conversion.
• The demonstrated performance metrics highlight the potential of this design for next-generation energy-constrained monitoring devices.